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k10p144m100sf2v2 k10 sub-family supports the following: mk10dx128vlq10, mk10dx128vmd10, mk10dx256vlq10, mk10dx256vmd10, mk10dn512vlq10, MK10DN512VMD10 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 100 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb program flash memory on non- flexmemory devices C up to 256 kb program flash memory on flexmemory devices C up to 256 kb flexnvm on flexmemory devices C 4 kb flexram on flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C multiple low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 16-channel dma controller, supporting up to 63 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C 128-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C two 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C two 12-bit dacs C two transimpedance amplifiers C three analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timer C two 2-channel quadrature decoder/general purpose timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C two controller area network (can) modules C three spi modules C two i2c modules C six uart modules C secure digital host controller (sdhc) C i2s module freescale semiconductor document number: k10p144m100sf2v2 data sheet: technical data rev. 3, 6/2013 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012C2013 freescale semiconductor, inc.
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table of contents 1 ordering parts ...........................................................................4 1.1 determining valid orderable parts......................................4 2 part identification ......................................................................4 2.1 description.........................................................................4 2.2 format ...............................................................................4 2.3 fields .................................................................................4 2.4 example ............................................................................5 3 terminology and guidelines ......................................................5 3.1 definition: operating requirement......................................5 3.2 definition: operating behavior ...........................................6 3.3 definition: attribute ............................................................6 3.4 definition: rating ...............................................................7 3.5 result of exceeding a rating ..............................................7 3.6 relationship between ratings and operating requirements......................................................................7 3.7 guidelines for ratings and operating requirements............8 3.8 definition: typical value.....................................................8 3.9 typical value conditions ....................................................9 4 ratings...................................................................................... 10 4.1 thermal handling ratings ................................................... 10 4.2 moisture handling ratings .................................................. 10 4.3 esd handling ratings .........................................................10 4.4 voltage and current operating ratings ............................... 10 5 general ..................................................................................... 11 5.1 ac electrical characteristics .............................................. 11 5.2 nonswitching electrical specifications ............................... 11 5.2.1 voltage and current operating requirements ......... 11 5.2.2 lvd and por operating requirements ................. 12 5.2.3 voltage and current operating behaviors .............. 13 5.2.4 power mode transition operating behaviors .......... 15 5.2.5 power consumption operating behaviors .............. 16 5.2.6 emc radiated emissions operating behaviors.......19 5.2.7 designing with radiated emissions in mind ........... 20 5.2.8 capacitance attributes .......................................... 20 5.3 switching specifications.....................................................20 5.3.1 device clock specifications ................................... 20 5.3.2 general switching specifications ........................... 21 5.4 thermal specifications ....................................................... 22 5.4.1 thermal operating requirements ........................... 22 5.4.2 thermal attributes ................................................. 22 6 peripheral operating requirements and behaviors .................... 23 6.1 core modules .................................................................... 23 6.1.1 debug trace timing specifications ......................... 23 6.1.2 jtag electricals .................................................... 24 6.2 system modules ................................................................ 27 6.3 clock modules ................................................................... 27 6.3.1 mcg specifications ............................................... 27 6.3.2 oscillator electrical specifications ......................... 29 6.3.3 32 khz oscillator electrical characteristics.............31 6.4 memories and memory interfaces ..................................... 32 6.4.1 flash electrical specifications................................32 6.4.2 ezport switching specifications ............................. 37 6.4.3 flexbus switching specifications ........................... 38 6.5 security and integrity modules .......................................... 41 6.6 analog ............................................................................... 41 6.6.1 adc electrical specifications ................................. 41 6.6.2 cmp and 6-bit dac electrical specifications ......... 49 6.6.3 12-bit dac electrical characteristics ..................... 52 6.6.4 voltage reference electrical specifications ............ 55 6.7 timers................................................................................56 6.8 communication interfaces ................................................. 56 6.8.1 can switching specifications ................................ 56 6.8.2 dspi switching specifications (limited voltage range).................................................................... 57 6.8.3 dspi switching specifications (full voltage range).58 6.8.4 inter-integrated circuit interface (i2c) timing ........ 60 6.8.5 uart switching specifications .............................. 61 6.8.6 sdhc specifications ............................................. 61 6.8.7 i2s/sai switching specifications............................62 6.9 human-machine interfaces (hmi)......................................68 6.9.1 tsi electrical specifications ................................... 68 7 dimensions ............................................................................... 69 7.1 obtaining package dimensions ......................................... 69 8 pinout ........................................................................................ 69 8.1 k10 signal multiplexing and pin assignments .................... 69 8.2 k10 pinouts ....................................................................... 75 9 revision history ......................................................................... 77 k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 3
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: pk10 and mk10 . 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k10 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory table continues on the next page... ordering parts k10 sub-family data sheet, rev. 3, 6/2013. 4 freescale semiconductor, inc.
field description values fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb ? 2m0 = 2 mb r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) ? mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mk10dn512zvmd10 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. terminology and guidelines k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 5
3.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf terminology and guidelines k10 sub-family data sheet, rev. 3, 6/2013. 6 freescale semiconductor, inc.
3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. terminology and guidelines k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 7
3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. terminology and guidelines k10 sub-family data sheet, rev. 3, 6/2013. 8 freescale semiconductor, inc.
3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v terminology and guidelines k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 9
4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life. 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm). 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components. 3. determined according to jedec standard jesd78, ic latch-up test. 4.4 voltage and current operating ratings ratings k10 sub-family data sheet, rev. 3, 6/2013. 10 freescale semiconductor, inc.
symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 185 ma v dio digital input voltage (except reset, extal, and xtal) C0.3 5.5 v v aio analog 1 , reset, extal, and xtal input voltage C0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all digital pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v bat rtc battery supply voltage C0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 11
5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital pin negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 i icaio analog 2 , extal, and xtal pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 +25 ma v odpu open drain pullup voltage level v dd v dd v 4 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in is less than v dio_min , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i icdio |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. additionally, extal and xtal are analog pins. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is less than v aio_min or greater than v aio_max , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i icaio |. the positive injection current limiting resistor is calculated as r=(v in -v aio_max )/|i icaio |. select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. open drain outputs must be pulled to vdd. general k10 sub-family data sheet, rev. 3, 6/2013. 12 freescale semiconductor, inc.
5.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 13
5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. 1 max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = -9ma ? 1.71 v v dd 2.7 v, i oh = -3ma v dd C 0.5 v dd C 0.5 v v output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2ma ? 1.71 v v dd 2.7 v, i oh = -0.6ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 10ma ? 1.71 v v dd 2.7 v, i ol = 5ma 0.5 0.5 v v 2 output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2ma ? 1.71 v v dd 2.7 v, i ol = 1ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i ina input leakage current, analog pins and digital pins configured as analog inputs ? v ss v in v dd ? all pins except extal32, xtal32, extal, xtal ? extal (pta18) and xtal (pta19) ? extal32, xtal32 0.002 0.004 0.075 0.5 1.5 10 a a a 3, 4 i ind input leakage current, digital pins ? v ss v in v il ? all digital pins ? v in = v dd ? all digital pins except ptd7 ? ptd7 0.002 0.002 0.004 0.5 0.5 1 a a a 4, 5 i ind input leakage current, digital pins ? v il < v in < v dd ? v dd = 3.6 v ? v dd = 3.0 v ? v dd = 2.5 v ? v dd = 1.7 v 18 12 8 3 26 49 13 6 a a a a 4, 5, 6 table continues on the next page... general k10 sub-family data sheet, rev. 3, 6/2013. 14 freescale semiconductor, inc.
table 4. voltage and current operating behaviors (continued) symbol description min. typ. 1 max. unit notes i ind input leakage current, digital pins ? v dd < v in < 5.5 v 1 50 a 4, 5 z ind input impedance examples, digital pins ? v dd = 3.6 v ? v dd = 3.0 v ? v dd = 2.5 v ? v dd = 1.7 v 48 55 57 85 k k k k 4, 7 r pu internal pullup resistors 20 35 50 k 8 r pd internal pulldown resistors 20 35 50 k 9 1. typical values characterized at 25c and vdd = 3.6 v unless otherwise noted. 2. open drain outputs must be pulled to v dd . 3. analog pins are defined as pins that do not have an associated general purpose i/o port function. 4. digital pins have an associated gpio port function and have 5v tolerant inputs, except extal and xtal. 5. internal pull-up/pull-down resistors disabled. 6. characterized, not tested in production. 7. examples calculated using v il relation, v dd , and max i ind : z ind =v il /i ind . this is the impedance needed to pull a high signal to a level below v il due to leakage when v il < v in < v dd . these examples assume signal source low = 0 v. 8. measured at v dd supply voltage = v dd min and vinput = v ss 9. measured at v dd supply voltage = v dd min and vinput = v dd + C digital input source z ind i ind 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsxrun recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz ? mcg mode: fei general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 15
table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. ? v dd slew rate 5.7 kv/s ? v dd slew rate < 5.7 kv/s 300 1.7 v / (v dd slew rate) s 1 ? vlls1 run 130 s ? vlls2 run 92 s ? vlls3 run 92 s ? lls run 5.9 s ? vlps run 5.0 s ? stop run 5.0 s 1. normal boot (ftfl_opt[lpboot]=1) 5.2.5 power consumption operating behaviors table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 37 38 63 64 ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v ? @ 25c ? @ 125c 46 47 58 77 63 79 ma ma ma 3, 4 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 20 ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 9 ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.12 ma 6 table continues on the next page... general k10 sub-family data sheet, rev. 3, 6/2013. 16 freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.71 ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.77 ma 8 i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.74 2.45 6.61 1.41 11.5 30 ma ma ma i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 83 425 1280 435 2000 4000 a a a i dd_lls low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 4.58 30.6 137 19.9 105 500 a a a 9 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 3.0 18.6 84.9 23 43 230 a a a 9 i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 2.2 9.3 41.4 5.4 35 128 a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 2.1 7.6 33.5 9 28 95.5 a a a i dd_vbat average current with rtc and 32khz disabled at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.19 0.49 2.2 0.22 0.64 3.2 a a a table continues on the next page... general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 17
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vbat average current when cpu is not accessing rtc registers ? @ 1.8v ? @ C40 to 25c ? @ 70c ? @ 105c ? @ 3.0v ? @ C40 to 25c ? @ 70c ? @ 105c 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 a a a a a a 10 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 3. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flexbus and flash clock. mcg configured for fei mode. 6. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. data reflects devices with 128 kb of ram. for devices with 64 kb of ram, power consumption is reduced by 2 a. for devices with 32 kb of ram, power consumption is reduced by 3 a. 10. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl general k10 sub-family data sheet, rev. 3, 6/2013. 18 freescale semiconductor, inc.
figure 2. run mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 144lqfp and 144mapbga symbol description frequency band (mhz) 144lqfp 144mapbga unit notes v re1 radiated emissions voltage, band 1 0.15C50 23 12 dbv 1, 2 v re2 radiated emissions voltage, band 2 50C150 27 24 dbv v re3 radiated emissions voltage, band 3 150C500 28 27 dbv v re4 radiated emissions voltage, band 4 500C1000 14 11 dbv v re_iec iec level 0.15C1000 k k 2, 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method. measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 19
2. v dd = 3.3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = 96 mhz, f bus = 48 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 5.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com. 2. perform a keyword search for emc design. 5.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 5.3 switching specifications 5.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 100 mhz f bus bus clock 50 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz table continues on the next page... general k10 sub-family data sheet, rev. 3, 6/2013. 20 freescale semiconductor, inc.
table 9. device clock specifications (continued) symbol description min. max. unit notes f lptmr_erclk lptmr external reference clock 16 mhz f flexcan_erclk flexcan external reference clock 8 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1, 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 12 6 36 24 ns ns ns ns 4 port rise and fall time (low drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 12 6 36 24 ns ns ns ns 5 general k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 21
1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75 pf load 5. 15 pf load 5.4 thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 5.4.2 thermal attributes board type symbol description 144 lqfp 144 mapbga unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 45 48 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 36 29 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 36 38 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 30 25 c/w 1 table continues on the next page... general k10 sub-family data sheet, rev. 3, 6/2013. 22 freescale semiconductor, inc.
board type symbol description 144 lqfp 144 mapbga unit notes r jb thermal resistance, junction to board 24 16 c/w 2 r jc thermal resistance, junction to case 9 9 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air), or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air). 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board. 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits, with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). 6 peripheral operating requirements and behaviors 6.1 core modules 6.1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 23
figure 3. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 4. trace data specifications 6.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 24 freescale semiconductor, inc.
table 13. jtag limited voltage range electricals (continued) symbol description min. max. unit j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 5. test clock input timing peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 25
j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 6. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 7. test access port timing peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 26 freescale semiconductor, inc.
j14 j13 tclk trst figure 8. trst timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules 6.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 3 %f dco 1, f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.3 3 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 27
table 15. mcg specifications (continued) symbol description min. typ. max. unit notes fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2, 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx32 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4, 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 7 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 7 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 50 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 8 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 28 freescale semiconductor, inc.
table 15. mcg specifications (continued) symbol description min. typ. max. unit notes t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation (f dco_t ) over voltage and temperature should be considered. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 9. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 16. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 29
table 16. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2, 3 c y xtal load capacitance 2, 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2, 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 30 freescale semiconductor, inc.
6.3.2.2 oscillator frequency specifications table 17. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1, 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3, 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32 khz oscillator dc electrical specifications table 18. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 31
table 18. 32khz oscillator dc electrical specifications (continued) symbol description min. typ. max. unit c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32 khz oscillator frequency specifications table 19. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2, 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk256k erase block high-voltage time for 256 kb 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 32 freescale semiconductor, inc.
6.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k read 1s block execution time ? 256 kb program/data flash 1.7 ms t rd1sec2k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk256k erase flash block execution time ? 256 kb program/data flash 122 985 ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512 t pgmsec1k t pgmsec2k program section execution time ? 512 bytes flash ? 1 kb flash ? 2 kb flash 2.4 4.7 9.3 ms ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 250 2000 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time ? control code 0x01 ? control code 0x02 ? control code 0x04 ? control code 0x08 200 70 70 150 150 30 s s s s t pgmpart64k t pgmpart256k program partition for eeprom execution time ? 64 kb flexnvm ? 256 kb flexnvm 138 145 ms ms t setramff t setram32k t setram64k t setram256k set flexram function execution time: ? control code 0xff ? 32 kb eeprom backup ? 64 kb eeprom backup ? 256 kb eeprom backup 70 0.8 1.3 4.5 1.2 1.9 5.5 s ms ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 s 3 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 33
table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr8b32k t eewr8b64k t eewr8b128k t eewr8b256k byte-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 385 475 650 1000 1800 2000 2400 3200 s s s s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 s t eewr16b32k t eewr16b64k t eewr16b128k t eewr16b256k word-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 385 475 650 1000 1800 2000 2400 3200 s s s s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 s t eewr32b32k t eewr32b64k t eewr32b128k t eewr32b256k longword-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 630 810 1200 1900 2050 2250 2675 3500 s s s s 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash high voltage current behaviors table 22. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 34 freescale semiconductor, inc.
6.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree32k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 4096 ? eeprom backup to flexram ratio = 32,768 35 k 315 k 1.27 m 10 m 80 m 175 k 1.6 m 6.4 m 50 m 400 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the flash memory module to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 35
while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom C 2 eeesplit eeesize eeesplit eeesize nvmcycd where ? writes_subsystem minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom allocated flexnvm for each eeprom subsystem based on depart; entered with the program partition command ? eeesplit flexram split factor for subsystem; entered with the program partition command ? eeesize allocated flexram based on depart; entered with the program partition command ? write_efficiency ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd data flash cycling endurance (the following graph assumes 10,000 cycles) peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 36 freescale semiconductor, inc.
figure 9. eeprom backup writes to flexram 6.4.2 ezport switching specifications table 24. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 37
ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 10. ezport timing diagram 6.4.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 25. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n, fb_cs n, fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 38 freescale semiconductor, inc.
2. specification is valid for all fb_ad[31:0] and fb_ta. table 26. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 13.5 ns 1 fb3 address, data, and control output hold 0 ns 1 fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n, fb_cs n, fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 39
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb5 fb4 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 11. flexbus read timing diagram peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 40 freescale semiconductor, inc.
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 12. flexbus write timing diagram 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 6.6 analog peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 41
6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 27 and table 28 are achievable on the differential pins adcx_dp0, adcx_dm0, adcx_dp1, adcx_dm1, adcx_dp3, and adcx_dm3. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 29 and table 30. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 27. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input resistance 2 5 k r as analog source resistance 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 42 freescale semiconductor, inc.
table 27. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool. r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pininput pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 13. adc input impedance equivalency diagram 6.6.1.2 16-bit adc electrical characteristics table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 . min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 43
table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 C94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 44 freescale semiconductor, inc.
table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c v temp25 temp sensor voltage 25 c 706 716 726 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. figure 14. typical enob vs. adc_clk for 16-bit differential mode peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 45
figure 15. typical enob vs. adc_clk for 16-bit single-ended mode 6.6.1.3 16-bit adc with pga operating conditions table 29. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2, 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k in+ to in- 4 r as analog source resistance 100 5 t s adc sampling time 1.25 s 6 table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 46 freescale semiconductor, inc.
table 29. 16-bit adc with pga operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 6.6.1.4 16-bit adc with pga characteristics with chop enabled (adc_pga[pgachpb] =0) table 30. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 a gain =64, v refpga =1.2v, v cm =0.1v 0.57 a table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 47
table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes g gain 4 ? pgag=0 ? pgag=1 ? pgag=2 ? pgag=3 ? pgag=4 ? pgag=5 ? pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 bw input signal bandwidth ? 16-bit modes ? < 16-bit modes 4 40 khz khz psrr power supply rejection ratio gain=1 -84 db v dda = 3v 100mv, f vdda = 50hz, 60hz cmrr common mode rejection ratio ? gain=1 ? gain=64 -84 -85 db db v cm = 500mvpp, f vcm = 50hz, 100hz v ofs input offset voltage 0.2 mv output offset = v ofs *(gain+1) t gsw gain switching settling time 10 s 5 dg/dt gain drift over full temperature range ? gain=1 ? gain=64 6 31 10 42 ppm/c ppm/c dg/dv dda gain drift over supply voltage ? gain=1 ? gain=64 0.07 0.14 0.21 0.31 %/v %/v v dda from 1.71 to 3.6v e il input leakage error all modes i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga 0.583 v 6 snr signal-to-noise ratio ? gain=1 ? gain=64 80 52 90 66 db db 16-bit differential mode, average=32 thd total harmonic distortion ? gain=1 ? gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 48 freescale semiconductor, inc.
table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes sfdr spurious free dynamic range ? gain=1 ? gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits ? gain=1, average=4 ? gain=1, average=8 ? gain=64, average=4 ? gain=64, average=8 ? gain=1, average=32 ? gain=2, average=32 ? gain=4, average=32 ? gain=8, average=32 ? gain=16, average=32 ? gain=32, average=32 ? gain=64, average=32 11.6 8.0 7.2 6.3 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 13.6 9.6 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100hz sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 31. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 49
table 31. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 50 freescale semiconductor, inc.
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 16. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 51
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cmp 10 11 vin level (v) figure 17. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 32. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature operating temperature range of the device c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 52 freescale semiconductor, inc.
6.6.3.2 12-bit dac operating behaviors table 33. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 330 a i dda_dach p supply current high-speed mode 1200 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0+100mv to v dacr ?100 mv 3. the dnl is measured for 0+100 mv to v dacr ?100 mv 4. the dnl is measured for 0+100mv to v dacr ?100 mv with v dda > 2.4v 5. calculated by a best fit curve from v ss +100 mv to v dacr ?100 mv 6. vdda = 3.0v, reference select set for vdda (dacx_co:dacrfs = 1), high power mode(dacx_c0:lpen = 0), dac set to 0x800, temp range from -40c to 105c peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 53
figure 18. typical inl error vs. digital code peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 54 freescale semiconductor, inc.
figure 19. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 34. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1, 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 55
table 35. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v v out voltage reference output factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.193 1.197 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1, 2 t stup buffer startup time 100 s v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 36. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 37. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 6.7 timers see general switching specifications. 6.8 communication interfaces peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 56 freescale semiconductor, inc.
6.8.1 can switching specifications see general switching specifications. 6.8.2 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 38. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcsn valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcsn invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8 ns ds6 dspi_sck to dspi_sout invalid 0 ns ds7 dspi_sin to dspi_sck input setup 14 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 20. dspi classic spi timing master mode peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 57
table 39. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 21. dspi classic spi timing slave mode 6.8.3 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 40. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bus ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 58 freescale semiconductor, inc.
table 40. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcsn valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcsn invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid -1.2 ns ds7 dspi_sin to dspi_sck input setup 19.1 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 22. dspi classic spi timing master mode table 41. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 24 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 3.2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 19 ns ds16 dspi_ss inactive to dspi_sout not driven 19 ns peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 59
first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 23. dspi classic spi timing slave mode 6.8.4 inter-integrated circuit interface (i 2 c) timing table 42. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 1 3.45 2 0 3 0.9 1 s data set-up time t su ; dat 250 4 100 2, 5 ns rise time of sda and scl signals t r 1000 20 +0.1c b 6 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 5 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 3. input signal slew = 10 ns and output load = 50 pf 4. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 5. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 60 freescale semiconductor, inc.
6. c b = total capacitance of the one bus line in pf. ? ? sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r figure 24. timing definition for fast and standard mode devices on the i 2 c bus 6.8.5 uart switching specifications see general switching specifications. 6.8.6 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 43. sdhc switching specifications num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\50 mhz fpp clock frequency (mmc full speed\high speed) 0 20\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 8.3 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 61
sd2 sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 25. sdhc timing 6.8.7 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.7.1 normal run, wait and stop mode performance over a limited operating voltage range this section provides the operating performance over a limited operating voltage for the device in normal run, wait and stop modes. table 44. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 62 freescale semiconductor, inc.
table 44. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) (continued) num. characteristic min. max. unit s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 26. i2s/sai timing master modes table 45. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ? multiple sai synchronous mode ? all other modes 21 15 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 63
table 45. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) (continued) num. characteristic min. max. unit s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 27. i2s/sai timing slave modes 6.8.7.2 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 46. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 64 freescale semiconductor, inc.
table 46. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) (continued) num. characteristic min. max. unit s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 20.5 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 28. i2s/sai timing master modes table 47. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ? multiple sai synchronous mode ? all other modes 24 20.6 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 65
table 47. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) (continued) num. characteristic min. max. unit s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 29. i2s/sai timing slave modes 6.8.7.3 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 48. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns table continues on the next page... peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 66 freescale semiconductor, inc.
table 48. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 30. i2s/sai timing master modes table 49. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 3 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 63 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 67
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 31. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 50. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 15 mhz 2, 3 f elemax electrode oscillator frequency 1 1.8 mhz 2, 4 c ref internal reference capacitor 1 pf v delta oscillator delta voltage 500 mv 2, 5 i ref reference oscillator current source base current ? 2 a setting (refchrg = 0) ? 32 a setting (refchrg = 15) 2 36 3 50 a 2, 6 i ele electrode oscillator current source base current ? 2 a setting (extchrg = 0) ? 32 a setting (extchrg = 15) 2 36 3 50 a 2, 7 pres5 electrode capacitance measurement precision 8.3333 38400 ff/count 8 pres20 electrode capacitance measurement precision 8.3333 38400 ff/count 9 pres100 electrode capacitance measurement precision 8.3333 38400 ff/count 10 maxsens maximum sensitivity 0.008 1.46 ff/count 11 res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 12 i tsi_run current added in run mode 55 a i tsi_lp low power mode current adder 1.3 2.5 a 13 peripheral operating requirements and behaviors k10 sub-family data sheet, rev. 3, 6/2013. 68 freescale semiconductor, inc.
1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. refchrg = 2, extchrg=0. 4. refchrg = 0, extchrg = 10. 5. v dd = 3.0 v. 6. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 7. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 8. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 10. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 11. sensitivity defines the minimum capacitance change when a single count from the tsi module changes. sensitivity depends on the configuration used. the documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (c ref * i ext )/( i ref * ps * nscn) the typical value is calculated with the following configuration: i ext = 6 a (extchrg = 2), ps = 128, nscn = 2, i ref = 16 a (refchrg = 7), c ref = 1.0 pf the minimum value is calculated with the following configuration: i ext = 2 a (extchrg = 0), ps = 128, nscn = 32, i ref = 32 a (refchrg = 15), c ref = 0.5 pf the highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. time to do one complete measurement of the electrode. sensitivity resolution of 0.0133 pf, ps = 0, nscn = 0, 1 electrode, extchrg = 7. 13. refchrg=0, extchrg=4, ps=7, nscn=0f, lpscnitv=f, lpo is selected (1 khz), and fixed external capacitance of 20 pf. data is captured with an average of 7 periods window. 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 144-pin lqfp 98ass23177w 144-pin mapbga 98asa00222d 8 pinout dimensions k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 69
8.1 k10 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport l5 rtc_ wakeup_b rtc_ wakeup_b rtc_ wakeup_b m5 nc nc nc a10 nc nc nc b10 nc nc nc c10 nc nc nc 1 d3 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda rtc_clkout 2 d2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 i2c1_scl spi1_sin 3 d1 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_ b sdhc0_dclk 4 e4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_ b sdhc0_cmd spi1_sout 5 e5 vdd vdd vdd 6 f6 vss vss vss 7 e3 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 8 e2 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 9 e1 pte6 disabled pte6 spi1_pcs3 uart3_cts_ b i2s0_mclk 10 f4 pte7 disabled pte7 uart3_rts_ b i2s0_rxd0 11 f3 pte8 disabled pte8 i2s0_rxd1 uart5_tx i2s0_rx_fs 12 f2 pte9 disabled pte9 i2s0_txd1 uart5_rx i2s0_rx_ bclk 13 f1 pte10 disabled pte10 uart5_cts_ b i2s0_txd0 14 g4 pte11 disabled pte11 uart5_rts_ b i2s0_tx_fs 15 g3 pte12 disabled pte12 i2s0_tx_ bclk 16 e6 vdd vdd vdd 17 f7 vss vss vss 18 h1 pte16 adc0_se4a adc0_se4a pte16 spi0_pcs0 uart2_tx ftm_clkin0 ftm0_flt3 19 h2 pte17 adc0_se5a adc0_se5a pte17 spi0_sck uart2_rx ftm_clkin1 lptmr0_ alt3 20 g1 pte18 adc0_se6a adc0_se6a pte18 spi0_sout uart2_cts_ b i2c0_sda pinout k10 sub-family data sheet, rev. 3, 6/2013. 70 freescale semiconductor, inc.
144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 21 g2 pte19 adc0_se7a adc0_se7a pte19 spi0_sin uart2_rts_ b i2c0_scl 22 h3 vss vss vss 23 j1 adc0_dp1 adc0_dp1 adc0_dp1 24 j2 adc0_dm1 adc0_dm1 adc0_dm1 25 k1 adc1_dp1 adc1_dp1 adc1_dp1 26 k2 adc1_dm1 adc1_dm1 adc1_dm1 27 l1 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 28 l2 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 29 m1 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 30 m2 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 31 h5 vdda vdda vdda 32 g5 vrefh vrefh vrefh 33 g6 vrefl vrefl vrefl 34 h6 vssa vssa vssa 35 k3 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 36 j3 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 37 m3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 38 l3 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 39 l4 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 40 m7 xtal32 xtal32 xtal32 41 m6 extal32 extal32 extal32 42 l6 vbat vbat vbat 43 vdd vdd vdd 44 vss vss vss 45 m4 pte24 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx ewm_out_b pinout k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 71
144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 46 k5 pte25 adc0_se18 adc0_se18 pte25 can1_rx uart4_rx ewm_in 47 k4 pte26 disabled pte26 uart4_cts_ b rtc_clkout 48 j4 pte27 disabled pte27 uart4_rts_ b 49 h4 pte28 disabled pte28 50 j5 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b/ uart0_col_ b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 51 j6 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 52 k6 pta2 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do 53 k7 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_ b ftm0_ch0 jtag_tms/ swd_dio 54 l7 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 55 m8 pta5 disabled pta5 ftm0_ch2 cmp2_out i2s0_tx_ bclk jtag_trst_ b 56 e7 vdd vdd vdd 57 g7 vss vss vss 58 j7 pta6 disabled pta6 ftm0_ch3 trace_ clkout 59 j8 pta7 adc0_se10 adc0_se10 pta7 ftm0_ch4 trace_d3 60 k8 pta8 adc0_se11 adc0_se11 pta8 ftm1_ch0 ftm1_qd_ pha trace_d2 61 l8 pta9 disabled pta9 ftm1_ch1 ftm1_qd_ phb trace_d1 62 m9 pta10 disabled pta10 ftm2_ch0 ftm2_qd_ pha trace_d0 63 l9 pta11 disabled pta11 ftm2_ch1 ftm2_qd_ phb 64 k9 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 i2s0_txd0 ftm1_qd_ pha 65 j9 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 i2s0_tx_fs ftm1_qd_ phb 66 l10 pta14 disabled pta14 spi0_pcs0 uart0_tx i2s0_rx_ bclk i2s0_txd1 67 l11 pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 68 k10 pta16 disabled pta16 spi0_sout uart0_cts_ b/ uart0_col_ b i2s0_rx_fs i2s0_rxd1 69 k11 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_ b i2s0_mclk pinout k10 sub-family data sheet, rev. 3, 6/2013. 72 freescale semiconductor, inc.
144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 70 e8 vdd vdd vdd 71 g8 vss vss vss 72 m12 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 73 m11 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 74 l12 reset_b reset_b reset_b 75 k12 pta24 disabled pta24 fb_a29 76 j12 pta25 disabled pta25 fb_a28 77 j11 pta26 disabled pta26 fb_a27 78 j10 pta27 disabled pta27 fb_a26 79 h12 pta28 disabled pta28 fb_a25 80 h11 pta29 disabled pta29 fb_a24 81 h10 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha 82 h9 ptb1 adc0_se9/ adc1_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_ phb 83 g12 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_ b ftm0_flt3 84 g11 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_ b ftm0_flt0 85 g10 ptb4 adc1_se10 adc1_se10 ptb4 ftm1_flt0 86 g9 ptb5 adc1_se11 adc1_se11 ptb5 ftm2_flt0 87 f12 ptb6 adc1_se12 adc1_se12 ptb6 fb_ad23 88 f11 ptb7 adc1_se13 adc1_se13 ptb7 fb_ad22 89 f10 ptb8 disabled ptb8 uart3_rts_ b fb_ad21 90 f9 ptb9 disabled ptb9 spi1_pcs1 uart3_cts_ b fb_ad20 91 e12 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19 ftm0_flt1 92 e11 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18 ftm0_flt2 93 h7 vss vss vss 94 f5 vdd vdd vdd 95 e10 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx fb_ad17 ewm_in 96 e9 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx fb_ad16 ewm_out_b 97 d12 ptb18 tsi0_ch11 tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_ bclk fb_ad15 ftm2_qd_ pha 98 d11 ptb19 tsi0_ch12 tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb 99 d10 ptb20 disabled ptb20 spi2_pcs0 fb_ad31 cmp0_out 100 d9 ptb21 disabled ptb21 spi2_sck fb_ad30 cmp1_out pinout k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 73
144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 101 c12 ptb22 disabled ptb22 spi2_sout fb_ad29 cmp2_out 102 c11 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28 103 b12 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg fb_ad14 i2s0_txd1 104 b11 ptc1/ llwu_p6 adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_ b ftm0_ch0 fb_ad13 i2s0_txd0 105 a12 ptc2 adc0_se4b/ cmp1_in0/ tsi0_ch15 adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_ b ftm0_ch1 fb_ad12 i2s0_tx_fs 106 a11 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_ bclk 107 h8 vss vss vss 108 vdd vdd vdd 109 a9 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11 cmp1_out 110 d8 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 fb_ad10 cmp0_out 111 c8 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_ bclk fb_ad9 i2s0_mclk 112 b8 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin i2s0_rx_fs fb_ad8 113 a8 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk fb_ad7 114 d7 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_ bclk fb_ad6 ftm2_flt0 115 c7 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl i2s0_rx_fs fb_ad5 116 b7 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda i2s0_rxd1 fb_rw_b 117 a7 ptc12 disabled ptc12 uart4_rts_ b fb_ad27 118 d6 ptc13 disabled ptc13 uart4_cts_ b fb_ad26 119 c6 ptc14 disabled ptc14 uart4_rx fb_ad25 120 b6 ptc15 disabled ptc15 uart4_tx fb_ad24 121 vss vss vss 122 vdd vdd vdd 123 a6 ptc16 disabled ptc16 can1_rx uart3_rx fb_cs5_b/ fb_tsiz1/ fb_be23_16_ b 124 d5 ptc17 disabled ptc17 can1_tx uart3_tx fb_cs4_b/ fb_tsiz0/ fb_be31_24_ b 125 c5 ptc18 disabled ptc18 uart3_rts_ b fb_tbst_b/ fb_cs2_b/ fb_be15_8_b pinout k10 sub-family data sheet, rev. 3, 6/2013. 74 freescale semiconductor, inc.
144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 126 b5 ptc19 disabled ptc19 uart3_cts_ b fb_cs3_b/ fb_be7_0_b fb_ta_b 127 a5 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_ b fb_ale/ fb_cs1_b/ fb_ts_b 128 d4 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_ b fb_cs0_b 129 c4 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx fb_ad4 130 b4 ptd3 disabled ptd3 spi0_sin uart2_tx fb_ad3 131 a4 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rts_ b ftm0_ch4 fb_ad2 ewm_in 132 a3 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_ b ftm0_ch5 fb_ad1 ewm_out_b 133 a2 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 134 m10 vss vss vss 135 f8 vdd vdd vdd 136 a1 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 137 c9 ptd8 disabled ptd8 i2c0_scl uart5_rx fb_a16 138 b9 ptd9 disabled ptd9 i2c0_sda uart5_tx fb_a17 139 b3 ptd10 disabled ptd10 uart5_rts_ b fb_a18 140 b2 ptd11 disabled ptd11 spi2_pcs0 uart5_cts_ b sdhc0_ clkin fb_a19 141 b1 ptd12 disabled ptd12 spi2_sck sdhc0_d4 fb_a20 142 c3 ptd13 disabled ptd13 spi2_sout sdhc0_d5 fb_a21 143 c2 ptd14 disabled ptd14 spi2_sin sdhc0_d6 fb_a22 144 c1 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 fb_a23 8.2 k10 pinouts the figure below shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 75
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 vdd 107 106 105 104 103 102 101 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 116 ptc11/llwu_p11 115 114 113 112 111 110 109 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 124 ptc17 123 122 121 120 119 118 117 ptc16 vdd vss ptc15 ptc14 ptc13 ptc12 132 ptd5 131 130 129 128 127 126 125 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc19 ptc18 140 ptd11 139 138 137 136 135 134 133 ptd10 ptd9 ptd8 ptd7 vdd vss ptd6/llwu_p15 144 143 142 141 ptd15 ptd14 ptd13 ptd12 ptb20 pta28 pta27 pta26 pta25 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb8 ptb7 pta29 ptb0/llwu_p5 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb21 pta24 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta11 pta10 pta9 pta8 pta7 pta6 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte28 pte27 pte26 pte25 pte24 vss vdd vbat extal32 xtal32 dac1_out/cmp0_in4/cmp2_in3/adc1_se23 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 pte18 pte17 pte16 vss vdd pte12 pte11 pte10 pte9 pte8 pte7 pte6 pte5 pte4/llwu_p2 vss vdd pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 adc1_dp1 adc0_dm1 adc0_dp1 vss pte19 adc0_se16/cmp1_in2/adc0_se21 adc1_se16/cmp2_in2/adc0_se22 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 adc1_dm1 figure 32. k10 144 lqfp pinout diagram pinout k10 sub-family data sheet, rev. 3, 6/2013. 76 freescale semiconductor, inc.
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a b c d e f g h j a b c d e f g h j 10 k k 10 11 11 l l 12 12 m m pta18 ptc8 ptc4/ nc ptc3/ ptc2 pta1 pta6 pta0 pte27 adc0_se16/ adc1_se16/ pte26 pte25 pta2 pta3 pta8 pta7 vss vss vssa vdda pte28 vss pte17 adc0_dm1 adc1_dm1 pga0_dm/ dac0_out/ dac1_out/ rtc vbat pta4/ pta9 pta11 pta12 pta13/ ptb1 pta27 ptb0/ ptb4 ptb5 vss vss vrefl vrefh pte11 pte12 pte19 pte18 pte16 adc0_dp1 adc1_dp1 pga0_dp/ pga1_dp/ pga1_dm/ vref_out/ pte24 nc extal32 xtal32 pta5 pta10 vss pta16 pta14 ptb3 pta29 pta26 pta17 pta15 pta19 reset_b pta24 pta25 pta28 ptb2 ptb6 ptb7 ptb8 ptb9 vdd vdd ptb17 ptb16 ptb10 ptb11 ptb19 ptb18 ptb22 ptb23 nc ptb20 ptb21 ptc5/ ptd8 ptc6/ ptc7 ptd9 nc ptc1/ ptc0 vss vss vdd vdd ptc13 ptc9 ptc11/ ptc10 ptc19 ptc15 ptc14 ptc18 ptd2/ ptd3 ptd10 ptd13 pte0 ptd1 ptc17 vdd vdd pte7 pte3 pte4/ pte8 pte9 pte10 pte6 pte5 pte1/ pte2/ ptd15 ptd14 ptd11 ptd12 ptc12 ptc16 ptd0/ ptd4/ ptd5 ptd6/ ptd7 llwu_p15 llwu_p14 llwu_p12 llwu_p8 llwu_p7 llwu_p11 llwu_p6 llwu_p13 llwu_p10 llwu_p1 llwu_p0 llwu_p9 llwu_p2 llwu_p5 cmp1_in2/ adc0_se21 llwu_p4 cmp2_in2/ adc0_se22 adc0_dp0/ adc1_dp3 adc0_dm0/ adc1_dm3 cmp1_in3/ adc0_se23 cmp0_in4/ cmp2_in3/ adc1_se23 llwu_p3 adc1_dp0/ adc0_dp3 adc1_dm0/ adc0_dm3 cmp1_in5/ cmp0_in5/ adc1_se18 _wakeup_b figure 33. k10 144 mapbga pinout diagram 9 revision history the following table provides a revision history for this document. table 51. revision history rev. no. date substantial changes 1 6/2012 initial public revision table continues on the next page... revision history k10 sub-family data sheet, rev. 3, 6/2013. freescale semiconductor, inc. 77
table 51. revision history (continued) rev. no. date substantial changes 2 12/2012 replaced tbds throughout. 3 6/2013 ? in esd handling ratings, added a note for ilat. ? updated "voltage and current operating requirements" table 1. ? updated i ol data for v ol row in "voltage and current operating behaviors" table 4 . ? updated wakeup times and t por value in "power mode transition operating behaviors" table 5. ? in "emc radiated emissions operating behaviors . . ." table 7, added a column for 144mapbga. ? in "16-bit adc operating conditions" table 27, updated the max spec of vadin. ? in "16-bit adc electrical characteristics" table 28, updated the temp sensor slope and voltage specs. ? updated inter-integrated circuit interface (i 2 c) timing. ? in sdhc specifications, added operating voltage row. revision history k10 sub-family data sheet, rev. 3, 6/2013. 78 freescale semiconductor, inc.
information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the app lication or use of an y product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differen t applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technica l experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. cortex-m4 is the trademark of arm limited. ? 2012?2013freescale semiconductor, inc. document number: k10p144m100sf2v2 rev. 3 06/2013

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